Various semiconductor devices have been designed, fabricated and mass-produced utilizing the well known Hall-effect technology. Hall-effect semiconductor devices are temperature-compensated magnetic field sensing products. Such components are best suited for use in extremely harsh environments and for detecting position in automotive, industrial and commercial applications, including robotics where the identification of objects and/or counting the rotations of gears is required. A typical Hall-effect device relies on a magnetic field in order to sense position and can be fabricated utilizing integrated circuit) technology. A Hall-effect device generally includes one or more Hall elements operable based on Hall-effect technology.
The Hall-effect refers to a measurable voltage that appears across a conductive material, for example, a thin layer of n-or-p-doped silicon, when an electric current flowing through the conductor is influenced by the magnetic field. Under these conditions a transverse voltage is generated perpendicular to the applied current due to balancing of Lorentz and electromagnetic forces. The Hall-effect element includes bias current providing contacts and voltage-signal sensing contacts that are disposed on the semiconductor. The sensing contacts of the Hall-effect element provides an output signal that is responsive to the magnitude of the magnetic field extending perpendicular to the surface of the thin conductive layer.
The majority of prior art Hall-effect devices produce an undesirable offset voltage, in response to mechanical stress due to anisotropic piezoresistance in silicon Hall cells. For example, most Hall devices are encapsulated in a suitable housing or package for protection of the Hall element. The Hall-effect device is typically mounted on a substrate and encapsulated in a protective body such as epoxy, plastic or the like. As the mounting substrate and the encapsulation material generally possesses different coefficients of thermal expansion and elastic moduli which are also different from the coefficient of thermal expansion and elastic modulus of silicon. Hence, mounting and encapsulation of the silicon chip results in mechanical stresses on the chip. Since silicon is piezoresistive, physical stresses placed on the chip alter its electrical resistance characteristics resulting in voltage offsets produced by mechanical stress rather than Hall-effect.
The offset voltage generally refers to an output voltage even in the absence of the magnetic field voltage, which occurs when there are physical inaccuracies and material non-uniformities. Similarly, process variations in the fabrication of the Hall-effect element may cause local variations in resistance. Further, unbalance in the subsequent amplifiers typically utilized with Hall-effect elements also can contribute to voltage offset. While the offset voltage is usually quite small, it can be large enough to affect the proper operation of the Hall-effect element.
A trimmer network is typically provided to balance the resistance variations. For example, the trimmer network may include a current mirror with trimmable degeneration resistors. The problem associated with these trimmer networks is that the trimmer networks with their associated compensation devices increase the size and complexity of the Hall-effect elements, both in terms of fabrication and operation. The trimming resistors formed in the integrated circuit chip cannot be utilized to further adjust voltage offsets after the device has been encapsulated. The prior art approaches are somewhat satisfactory for gross adjustments to predeterminable voltage offsets but they suffer from lack of reproducibility and sensitivity to packaging process parameters.
Based on the foregoing it is believed that a need exists for an improved Hall-effect device with merged complementary structure in order to cancel stress induced offsets as disclosed in further detail herein.